This invention relates generally to communications and, more particularly, to packet communications systems.
The Optical Internetworking Forum's (OIF) System Packet Interface Level 4 Phase 2 (SPI-4.2) defines an interface for the interconnection of Physical Layer devices to Link Layer devices for packet and cell transfer over OC-192 ATM (Asynchronous Transfer Mode) and Packet over SONET/SDH (POS), 10 Gb/s (Giga bit per second) Ethernet, as well as general purpose 10 Gb/s communication links. (For additional information see “System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer Device,” Optical Internetworking Forum, January 2001.)
The receive module for the Link Layer (hereinafter simply referred to as the SPI-4.2 receiver, or receiver) monitors the SPI-4.2 interface data bus, and is responsible for processing and storing received data.
As a result of the 10 Gb/s aggregate data bandwidth of the SPI-4.2 interface, the receiver must perform high-speed data processing—i.e., processing and storing 16 bit data words at rates typically up to 800 MHz (400 MHz, Double Data Rate (DDR)). For example, the SPI-4.2 interface requires state-based processing at these high data rates, where the states of the receiver and the state transitions are based on received control/data words. In addition, this state-based processing by the receiver involves monitoring received data for packet flow indications, changing the state according to these indications, and storing the received data according to the previous and current states. The SPI-4.2 standard also defines “shared” control words, which simultaneously end the previous transfer and start a new transfer.
In addition to the above-mentioned state-based processing, alignment issues must be considered in the context of this high-speed environment. In particular, there must be alignment of the Channel Address (ADDR), Start-of-Packet (SOP), End-of-Packet (EOP), Modulo (MOD) and Error (ERR) indications with respect to the corresponding data word. In particular, the received data presented to the Link Layer must have the ADDR and SOP indications aligned with the first word of the packet, while the EOP, MOD and ERR indications must be aligned with the last word of the packet. However, the ADDR and SOP indications on the SPI-4.2 interface precede the first data word, while the EOP, MOD and ERR indications follow the last data word.